October 2018 Issue Vol.8 No.10
Wireless Sensors in Industrial Automation
https://ia601507.us.archive.org/21/items/vol8no1001/vol8no1001.pdf
Varshitha Prakash
Research Scholar, Instrument Technology, Andhra University, Visakhapatnam, India
Dr.M.Ramesh Patnaik
Assistant Professor, Instrument Technology, Andhra University, Visakhapatnam, India
Abstract:
The advancement in technology led to the development of wireless sensors which are available now in smaller size, smarter, cheaper and lighter. Industrialists identified that wireless sensors exhibit different advantages like low cost, convenience, safer and more importantly they see it as an enabler of completely new improvement in communication purpose as reliable transmission can take place which increases their present production and manufacturing process. However, in industrial environment, while transmitting the data many challenges occur because of numerous noise sources so, the channel conditions may vary. In this paper an overview of wireless sensors and the problem faced with respect to channel is presented.
Keywords:Wireless Sensors, Wireless Communication, Industrial Automation, Wireless Channel, Coding Technique.
A Self-Cascode Based Subthreshold Positive Feedback Adiabatic Logic For Ultra Low Power Applications
https://ia601502.us.archive.org/12/items/vol8no1002/vol8no1002.pdf
Vivek Jain
Research Scholar, E&TC Department, IET-DAVV, Indore (M. P.), India
Sanjiv Tokekar
Professor, E&TC Department, IET-DAVV, Indore (M. P.), India
Vaibhav Neema
Asst. Professor, E&TC Department, IET-DAVV, Indore (M. P.), India
Abstract:
The self cascode positive feedback adiabatic logic (SC-PFAL) is reported as a promising candidate for low power applications. In this paper concept of self cascoding of transistor is applied to adiabatic logic working in sub-threshold region to enhance the energy efficiency of the gates. A library of gates based on proposed logic is designed and simulated using 70nm technology model file available from predictive technologies. Application of self cascode to adiabatic logic gates is explored for the first time in the literature. The spice simulation results illustrate these logic cells have significant improvement in terms of power consumption over their original PFAL and other adiabatic logic counterpart when operated at low frequency.
Keywords:Adiabatic logic, Self-cascode, PFAL, Ultra-low power.
Read complete October2018
Vivek Jain
Research Scholar, E&TC Department, IET-DAVV, Indore (M. P.), India
Sanjiv Tokekar
Professor, E&TC Department, IET-DAVV, Indore (M. P.), India
Vaibhav Neema
Asst. Professor, E&TC Department, IET-DAVV, Indore (M. P.), India
Abstract: The self cascode positive feedback adiabatic logic (SC-PFAL) is reported as a promising candidate for low power applications. In this paper concept of self cascoding of transistor is applied to adiabatic logic working in sub-threshold region to enhance the energy efficiency of the gates. A library of gates based on proposed logic is designed and simulated using 70nm technology model file available from predictive technologies. Application of self cascode to adiabatic logic gates is explored for the first time in the literature. The spice simulation results illustrate these logic cells have significant improvement in terms of power consumption over their original PFAL and other adiabatic logic counterpart when operated at low frequency.
Keywords:Adiabatic logic, Self-cascode, PFAL, Ultra-low power.